AMD EPYC Venice 9006: up to 256 cores per socket

The key difference of EPYC 9006 (Venice) is mainly the 256 cores per socket. This is three times more than in the previous EPYC 9005. Among other peculiarities are double memory bandwidth and a new PCIe 6.0 I/O subsystem. In addition to this, the updated Zen 6 microarchitecture also plays a huge role.

Exploring the Technical Features of the New Series

AMD decided to divide the lineup into a couple of various use cases based on 2 main types of sockets. A much broader range of tasks is covered by the new series, and that is a huge step which can be compared with a shift to separate I/O die architecture.

EPYC 9006 processors are based on Zen 6c and Zen 6 architecture. Practically, they are almost identical and don’t need any specific software optimization for functioning together. The major difference is that they are oriented towards various performance targets and market segments.

Zen 6 cores are created for the achievement of higher clock speed, whereas Zen 6c takes up less die area and is optimized for high packing density. Zen 6c doesn’t have support for SD V-Cache, and its operating frequencies are a little lower.

AMD claims that the Zen 6 architecture has a 20% increase in IPC when compared with Zen 5. Such increases are measured in enterprise workloads. Whereas an IPC increase of almost 31% in AI tasks is even more impressive.

Such huge improvements are achieved due to changes in instruction set architecture. For instance, AVX instructions for INT8, integer FMA operations, and format conversions. New instructions for bitwise matrix multiplication have also been added to AVX-512. In addition to this, three new kernel instructions designed for virtualization have been added; the most impactful one is FRED.  

A significant impact on the performance characteristics was also achieved by enlarging the micro-operation cache. The total op-cache capacity has increased to 6,750 instructions, and that is almost 13% more. Whereas the throughput has increased from 12 to almost 18 operations per clock cycle.

AMD has also increased L3 cache in the compact chiplets. Each core within the CCD of Zen 6c now has 4 MB of L3 cache. When talking about the major difference between the CCD for Zen 6c and Zen 6, the first variant has a max frequency of 4.1 GHz, whereas in Zen 6, the CCD reaches 5.3 GHz.

Specific updates are also made in the I/O die (IOD), which includes PCIe controllers, memory controllers, and the RoT module. The new approach to the manufacturing of the die is now based on TSMC’s 6-nm process. The main change in the IOD division is in two dies with support for 8 DDR5 channels.  

The connection between IOD crystals and CCD is now made via tiny silicon bridges so that CCD can be placed right next to IOD. Such an approach helps to minimize power consumption and reduces latency. Despite the obvious benefits, it may have some impact on cost.

Both single- and dual-socket configurations are used in the Venice SP7 platform. The transition to the dual-socket configuration needs the allocation of some PCIe lanes from each processor.

Due to the obvious shortage on the memory market, Venice platform uses specific technologies for the minimization of spending connected with DRAM usage. For instance, support for the CXL standard provides capabilities for memory expansion. Also, MEXT technologies are effectively utilized for the expansion of available memory via software tools.  

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