IBM and Siemens Prepare Engineers to Design Chips Using 0.7 nm Technology

IBM and Siemens have joined forces to advance chip design tools based on the Nanostack architecture.

The companies aim to prepare engineers to work with 0.7 nm technology, which could increase transistor density and reduce the power consumption of future chips.

Nanostack Technology and Its Benefits

The Nanostack architecture, also known as CFET, involves stacking n-type and p-type transistors vertically rather than placing them side by side. This approach allows more efficient use of chip area and increases component density.

IBM estimates the technology could fit about 100 billion transistors on a 150 mm² chip (nearly twice as many as a 2 nm process). The company also anticipates a potential 50% performance improvement or a 70% reduction in power consumption compared with 2 nm chips.

Not Without Challenges: The Complexities of the New Design

However, vertical transistor stacking makes chip design more complex due to electrical resistance and thermal interactions between components. To address these challenges, IBM plans to release a preliminary version of a Process Design Kit (PDK).

The kit will include libraries of standard logic cells and SRAM arrays, allowing engineers to test circuit designs and evaluate layout density, performance, and power consumption before manufacturing begins.

Siemens to Support EDA Development

Siemens will help adapt electronic design automation (EDA) tools to the new architecture. The company became a major player in this market after acquiring Mentor Graphics in 2017 for $4.5 billion.

The collaboration is also expected to involve chip designers, equipment manufacturers, and research organizations. 

The preliminary PDK is scheduled for release in the first quarter of 2027, while IBM expects the technology to be implemented in practice by 2031 at the latest.