Intel Reveals Next-Generation Massive AI Chip

Intel published a technical document outlining its strategy for developing and implementing new-generation hardware for AI applications. The highlight of the presentation was an actual sample of a system-in-package (SiP), the size of eight standard chip photomasks. This system is already production-ready.

Chip Architecture

As mentioned, the chip is equivalent in size to eight standard photomasks. It includes 4 powerful tiles (likely built on the 18A process), 12 stacks of high-speed HBM4 memory, and two I/O blocks for faster data transfer.

The presented build is significantly different from similar technologies from companies like TSMC. The main distinction is a multi-level design capable of integrating compute blocks, high-speed memory stacks, and fast inter-chip connections. Intel uses EMIB-T bridges with built-in through-holes, allowing signals and power to move freely both horizontally and vertically. This enables stacking compute blocks into a multilayer structure with maximum contact density.

It’s important to note that this is not yet a functioning AI accelerator, but a test chip designed to demonstrate the potential of AI processors’ build.

​Improved Energy Efficiency

Intel implemented several technologies to improve energy efficiency, including:

• PowerVia, which supplies power from the back of the tile.
• Integrated Voltage Regulators (IVR),
• Multi-level capacitors (eDTC and Omni MIM) for stabilizing power under high load.

Market Signal

The demonstration of the test AI chip also serves as a marketing move. Intel is showing clients that it has the capabilities to produce chips that outperform current competitors and is aiming to position itself as a leader in AI hardware development.

Regarding the chip itself, it represents another step towards energy-efficient data centers and the processing of complex machine learning and generative AI models.