At the IEEE International Electron Devices Conference (IEDM), Intel presented a next-generation 3D Stacked CMOS Transistor featuring the power supply and direct contact on the back side to reach better performance and scaling on next-generation chips.
The company also reported about making several breakthroughs in the development and research in the power back area and demonstrated successful large-scale, three-dimensional monolithic integration of silicon transistors with gallium nitride (GaN) transistors on a single 300-mm wafer.
Among other things, the Intel research team determined the main directions required to continue scaling through efficient transistor fusion.
In particular, they found a way to place complementary field-effect transistors (CFETs) vertically with reduced gate pitch to 60 nm to achieve better area usage.
The first implementation of the Intel PowerVia internal power supply enter will be set for production in 2024.
