Samsung's First Memory Chip Based on Sub-10-nm Technology

Samsung Electronics recently developed the first functional DRAM chip based on sub-10-nm technology.

Lithography in the semiconductor industry

Until recently, manufacturers in the semiconductor industry were mastering 10-nm process technologies, which are ranked in the following order: 1x, 1y, 1z, 1a, 1b, 1c, and 1d. Samsung engineers have successfully created the first DRAM chip prototype using the 10a-generation process. The feature sizes will range from 9.5 to 9.7 nm.

The next phase involves the use of this new technology in 2028 for the production of memory chips. The 10a, 10b, and 10c technologies will utilize a 4F2 cell architecture as well as vertical-channel transistors. With the subsequent 10d technology, a transition to 3D DRAM is planned.

The company may face certain risks when implementing 10a, which could be related to the increased density of memory cell placement. This structure implies a 30–50% increase in cell size. In addition to obvious layout changes related to capacitor placement and the fabrication of peripheral circuits on a separate die, there will also be changes in the chemical composition of the elements. Transistor channels will be made of zinc, gallium, and indium oxide.

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