AMD Plans to Accelerate L2 Cache in Future Ryzen CPUs

AMD is planning a radical architectural update for future Ryzen chips using vertical stacking. This approach is expected to deliver higher performance and improved efficiency in upcoming Ryzen X3D processors.

New Technology — “Balanced Latency”

AMD has filed a patent for a technology called Balanced Latency Stacked Cache, designed to address data access latency. The new L2 cache design reduces access latency from 14 to 12 cycles per 1 MB.

While this may seem like a minor improvement, saving even a few cycles can significantly impact how quickly cores receive commands, as well as overall performance and energy efficiency. Thanks to the vertical layout and centrally placed interconnects, the new processors gain a notable speed boost.

Why Does This Matter?

Although the title of the fastest processor at CES 2026 went to the Ryzen 7 9850X3D, the introduction of 3D L2 cache will allow future processors to handle workloads such as graphically complex games better. Even a two-cycle reduction can result in a noticeable increase in FPS.

Release Timeline

The patent is currently in the development stage, meaning AMD is experimenting with prototypes. Having a patent does not guarantee that the technology will reach the market soon, but it does provide insight into the direction of improvements the company is pursuing.