Insights about Zen 6 architecture and AMD EPYC processors

Recently, AMD shared some details regarding the new EPYC, together with information about Zen 6 architecture. Now, we can get some ideas about the potential capabilities of next-gen processors.

Zen 6 architectural innovations

The key improvement of the new architecture is in the increased component density. Zen 6 gets 12 high-performance cores and 48 MB of L3 cache placed on a CCD chiplet. Such designs create new perspectives for getting 24-core Ryzen processors using 2 of such chiplets. When compared with Zen 5, one chiplet could only include 8 cores and 32 MB of L3 cache.

12 cores that are placed on one chiplet can significantly minimize latency penalty during data exchange in gaming. In addition to this, there are claims of a significant increase in IPC. The IPC gain in server workloads and AI tasks has almost reached 27%.

In Zen 6 architecture, there are also some improvements to the branch prediction system where a 64-entry return address stack is added, queues are expanded, and up to 2 branch predictions can be processed per clock cycle. That means delays caused by incorrect prediction can be minimized.

The new architecture can give the opportunity to release 12-core Ryzen X3D on a single die. The possibility of 96 MB 3D V-Cache integration on top of the built-in 48 MB L3 cache has already been demonstrated in Venice-X chips. Such a combination can give 144 MB of L3 cache per 12-core chiplet.

Real performance gains in gaming from new Ryzen desktops are not yet clear. So, let’s wait for the actual independent benchmark results. However, AMD claims that the new EPYC delivers support for AI tasks even further than just answering questions, and we can check that information soon.   

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